Static Timing Analysis (STA) Engineer

LeadIC Design

Experience: 4+ yrs
Location: Bengaluru
Job type: Full-time

Required skills

STA
PrimeTime
Timing Closure

Nice to have

Full-Chip STA
SDC

About the role

Lead/Staff STA Engineer responsible for pre-layout and post-layout STA, block-level and full-chip timing signoff, SDC constraints, MCMM, OCV/AOCV/POCV, setup/hold closure, clock analysis and signoff. Strong PrimeTime and Tcl experience required. Work closely with RTL, PD, DFT and cross-site teams through tapeout.

About LeadIC Design

Founded in 2018, LeadIC has evolved into a trusted partner for global semiconductor companies, supporting the complete chip development lifecycle with deep technical capability, strong execution ownership, and flexible engagement models. With engineering teams across India and Canada.

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