We are looking for a SoC Design Verification Engineer with strong hands-on experience in PCIe Gen5 protocol verification.
The candidate will work on pre-silicon verification of PCIe functionality at the IP, subsystem, and SoC/full-chip levels using SystemVerilog and UVM.
Key Responsibilities:
- Develop verification plans and test scenarios for PCIe Gen5.
- Build and maintain SystemVerilog/UVM verification environments.
- Verify PCIe protocol functionality including LTSSM, link training, TLP, DLLP, enumeration, configuration, and error handling.
- Perform protocol compliance and functional verification.
- Debug complex PCIe protocol and RTL issues.
- Develop assertions and functional coverage.
- Execute regressions and drive coverage closure.
- Work closely with RTL, architecture, firmware, and other verification teams.
- Support verification sign-off at SoC/full-chip level.
Mandatory:
- Strong hands-on PCIe Gen5 protocol verification experience.
- Strong SystemVerilog/UVM experience.
- SoC/full-chip pre-silicon verification experience.
- Strong protocol debugging experience.
