3+ years of experience in VLSI layout verification / physical verification.
Hands-on experience in DRC, LVS, ERC, antenna, and density checks.
Strong expertise in Siemens Calibre or equivalent physical verification tools.
Experience debugging LVS shorts, opens, device mismatches, connectivity issues, and rule violations.
Good understanding of CMOS layout, device extraction, and foundry design rules.
Scripting experience in Perl/Python/Shell/TCL.
Experience supporting block/IP-level signoff and tape-out milestones
