We are looking for a Senior VLSI Physical Design Engineer with 5+ years of hands-on experience in the complete ASIC Physical Design flow from Netlist to GDSII. The candidate must have strong hands-on expertise in Cadence Innovus, including floorplanning, power planning, placement, CTS, routing, and physical optimization. The role requires experience in timing analysis and setup/hold timing closure, along with a strong understanding of MMMC, SDC, LEF/DEF, Liberty, and SPEF. Candidates should be experienced in resolving congestion, DRC, LVS, antenna, IR drop, and EM issues, as well as PPA optimization and clock-tree optimization. Good knowledge of STA using Cadence Tempus or Synopsys PrimeTime, Tcl scripting, and Linux/Unix is required. The candidate should also be capable of debugging physical-design issues and collaborating with RTL, Synthesis, STA, and Verification teams. Experience with advanced technology nodes will be an added advantage.
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