We are looking for a Senior VLSI Physical Design Engineer with 5+ years of hands-on experience in ASIC/VLSI Physical Design. The candidate must have strong hands-on experience with Cadence Innovus and the complete Physical Design flow from Netlist to GDSII.
The role involves Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), Routing, Physical Optimization, STA, and Timing Closure. The candidate should be experienced in debugging physical design issues and optimizing designs for Power, Performance, and Area (PPA).
Key Responsibilities
- Execute the complete ASIC Physical Design flow from Netlist to GDSII.
- Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Optimization using Cadence Innovus.
- Analyze and resolve Setup and Hold timing violations.
- Perform timing analysis and timing closure using STA tools.
- Work with MMMC scenarios and SDC timing constraints.
- Debug and resolve congestion, DRC, antenna, IR drop, and EM issues.
- Perform clock tree synthesis and clock optimization.
- Optimize designs for Power, Performance, and Area (PPA).
- Analyze physical design inputs and outputs including LEF, DEF, Liberty, SPEF, and timing constraints.
- Develop and debug Tcl scripts for Physical Design automation.
- Work in a Linux/Unix environment.
- Collaborate with RTL, Synthesis, STA, and Verification teams to resolve design issues.
- Support ECO implementation and physical/timing optimization as required.
