About the Role
Machina is a simulation platform that measures how well AI agents do real engineering work. Its team builds evaluations and reinforcement-learning (RL) environments in which agents design parts, close timing on chips, and run engineering software, and then judges where that work holds up and where it fails. Each role below is a hands-on engineering seat, not a research or ML seat. You bring the domain judgment of a working engineer; Machina brings the AI infrastructure. Post-training or ML experience is a plus, never a requirement. You will bring chip-design expertise to Machina's engineering evaluations and RL environments. The best evidence of fit is a real project where you carried a design from RTL toward implementation.
Responsibilities
• Design engineering tasks that mirror real projects in your discipline • Write reference solutions and grading criteria that a senior engineer would agree with • Review agent outputs (models, designs, calculations, code) and pinpoint exactly where the engineering goes wrong • Turn recurring failure patterns into new evaluations and RL environments • Work with the engineering and research team to tune environments built on tools such as SolidWorks, EDA suites and simulation solvers • Build evaluation tasks across the digital design flow: RTL, verification, synthesis, physical design and sign-off • Write reference RTL, testbenches and constraints, and define how agent outputs are graded • Review agent-generated designs and pinpoint functional bugs, timing violations and poor power, performance and area (PPA) choices • Set up and maintain EDA-based environments where agents run real tool flows • Turn common agent failure modes into new, harder evaluation tasks
Must Have
• Mid level, 3–5 years of hands-on experience • B.E./B.Tech or M.Tech in Electrical, Electronics or VLSI engineering • 3–5 years of ASIC or FPGA design experience • Strong RTL skills in Verilog, SystemVerilog or VHDL • Design verification experience: testbenches, UVM or similar, coverage and debug • Working knowledge of EDA flows from Synopsys, Cadence, Siemens or AMD/Xilinx Vivado and Intel Quartus • Understanding of synthesis, place-and-route, static timing analysis and timing closure • Sound judgment on PPA trade-offs • At least one project taken from specification through to implementation or tape-out
Nice to Have
• Post-training or ML experience • Open-source flow experience (Yosys, OpenROAD, Verilator, cocotb) • Scripting in Python, Tcl or Perl for flow automation • Exposure to post-training, AI evaluations or RL environments