Formal Verification Engineer
SiFive
- Salary
- ₹24 - 40 LPA
- Experience
- 5+ yrs
- Location
- India, Bengaluru, Ahmedabad, Gujarat, India, Hyderabad, Telangana, India
About the role
Looking for Formal verification engineer with atleast 5 years of experience. Should have worked on end-to-end exhaustive sign-off of complex blocks. Brownie points for having a CPU background, or interconnect (bridges, AMBA protocol, CXL) or NoC.
Responsibilities:
Identify blocks suitable for applying Formal Verification
Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics
Implementation and maintenance of Formal Verification environments in Chisel
Applying various FV techniques to reduce complexity and prove correctness of DUT
Debugging RTL to identify causes of failure scenarios
Guide and train team members on effective usage of Formal Verification tools
Develop/modify scripts to automate the verification process
Review formal setups and proofs with design and verification teams
Maintain and extend assertion libraries
Requirements:
5+ years of experience in Formal Verification of Digital Hardware Design
Extensive experience with Formal Abstraction Techniques and sign-off process
Familiarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold
Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ System Verilog
Knowledge of Object-oriented Programming is a plus
A keen interest in Processors and Digital systems
Strong reasoning skills and excellent attention to detail
Good inter-personal and teamwork skills!
Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering
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