Job Title: Senior SoC/Full-Chip Design Verification Engineer – GLS / SV-UVM
Must-have skills:
- Gate-Level Simulation (GLS) — Mandatory
- SystemVerilog (SV)
- UVM
- Verilog
- Pre-Silicon Verification
- SoC / Full-Chip Verification
- Digital Circuits
- Debug & Regression
Good-to-have skills:
- DRAM / Memory Controller Verification
- Assertions / SVA
- CMOS Concepts
- Digital/Analog Circuits
- Low-power verification
- Scripting / Automation
- Experience with industry-standard simulation and verification tools
Mandatory Requirement:
Candidates must have hands-on experience with Gate-Level Simulation (GLS). GLS experience is a deal-breaker for this position
