Design Verification Engineer – GLS
LeadIC Design
- Experience
- 4+ yrs
- Location
- Hyderabad
- Job type
- Full-time
Required skills
- Gate Level Simulation
- SystemVerilog
- Universal Verification Methodology - UVM
About the role
Job Title: Senior SoC/Full-Chip Design Verification Engineer – GLS / SV-UVM
Must-have skills:
- Gate-Level Simulation (GLS) — Mandatory
- SystemVerilog (SV)
- UVM
- Verilog
- Pre-Silicon Verification
- SoC / Full-Chip Verification
- Digital Circuits
- Debug & Regression
Good-to-have skills:
- DRAM / Memory Controller Verification
- Assertions / SVA
- CMOS Concepts
- Digital/Analog Circuits
- Low-power verification
- Scripting / Automation
- Experience with industry-standard simulation and verification tools
Mandatory Requirement:
Candidates must have hands-on experience with Gate-Level Simulation (GLS). GLS experience is a deal-breaker for this position
About LeadIC Design
Founded in 2018, LeadIC has evolved into a trusted partner for global semiconductor companies, supporting the complete chip development lifecycle with deep technical capability, strong execution ownership, and flexible engagement models.
With engineering teams across India and Canada location.
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