Senior Emulation / Pre-Silicon Validation Engineer
We are looking for an experienced Emulation Engineer with expertise in Cadence Palladium platforms to support ASIC/SoC pre-silicon validation. The ideal candidate should have strong experience in Palladium compilation flows, transactor development, SoC debug, and hardware/software co-validation.
Responsibilities
- Develop and maintain Palladium emulation environments
- Support Palladium build, compilation, partitioning, and debug flows
- Develop SystemC/C++ transactors and reference models
- Enable ICE and Virtual Interface (VIF) based validation
- Debug hardware/software integration issues
- Work closely with RTL, Verification, Firmware, and Architecture teams
- Analyze functional issues and improve validation efficiency
Required Skills
- 6+ years of ASIC/SoC emulation or pre-silicon validation
- Strong expertise with Cadence Palladium (XP, Z1, Z2 or Z3)
- Experience with Palladium compilation, advanced clocking, ICE and VIF
- Strong SystemC and C/C++ programming
- Python, TCL, Perl and Shell scripting
- Good understanding of SoC architecture
- Experience with AXI and standard interfaces such as PCIe, DDR, USB and SPI
Preferred Skills
- ZeBu, Veloce or Protium
- FPGA prototyping (HAPS/Xilinx)
- UVM
- Lauterbach, JTAG, CoreSight
- ARM/x86 platforms
- Networking ASICs
- Firmware validation and embedded software bring-up
