ADROITEC SYSTEMS PVT LTD
Website:
adroitecsys.com
Job details:
Company Description Adroitec Systems Pvt Ltd is a Bengaluru-based design and services company specializing in end-to-end semiconductor solutions from RTL design to GDS. The organization is committed to delivering high-quality results on time while keeping customers closely informed on project progress. With a team of highly skilled developers and engineers, Adroitec focuses on optimizing Power, Performance, and Area (PPA) metrics to provide robust, reliable chip design outcomes. The company offers turnkey project execution, resource augmentation, and point services in areas such as Physical Design, Physical Verification, Verification, DFT, Timing, and mission-critical tapeout tasks. Its team brings combined experience across 50+ chip tapeouts, supporting clients from concept to silicon.
Role Description The PD Engineer role is a full-time, on-site position based in Bengaluru South. The PD Engineer will work on physical design implementation flows from RTL to GDS, including floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure for complex SoCs and ASIC designs. Responsibilities include running and analyzing STA, resolving timing, congestion, and DRC/ LVS issues, and collaborating closely with front-end design, verification, and DFT teams to ensure clean handoffs and sign-off quality. The role involves preparing documentation, maintaining design databases, supporting mission-critical tapeouts, and contributing to continuous flow and methodology improvements. The PD Engineer will also participate in design reviews, help estimate efforts, and support customer communication as required.
Qualifications
- Strong expertise in physical design implementation, including floorplanning, placement, CTS, routing, and timing closure using industry-standard EDA tools (e.g., Cadence, Synopsys, or Mentor).
- Solid understanding of Static Timing Analysis, signal integrity, power integrity, and experience resolving timing, noise, and EM/IR issues.
- Hands-on experience in physical verification flows, including DRC, LVS, antenna checks, and manufacturability (DFM) requirements.
- Knowledge of RTL-to-GDS flows, low-power design techniques, clock domain management, and familiarity with PPA optimization methodologies.
- Proficiency with scripting languages (such as Tcl, Python, or Perl) to automate design tasks and enhance productivity.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related discipline, or equivalent practical experience.
- Ability to work collaboratively in cross-functional teams, communicate clearly with stakeholders, and manage tasks in time-sensitive tapeout environments.
- Prior experience on tapeout projects, exposure to advanced technology nodes, and understanding of SoC/ASIC architectures are highly beneficial.
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