Tessolve
Website:
tessolve.com
Job details:
Company Description Tessolve is a global technology services company offering integrated pre-silicon and post-silicon expertise to deliver turnkey solutions for silicon bring-up and product realization. With more than 3,800 team members and advanced silicon and system testing labs, Tessolve provides comprehensive hardware and software capabilities, including full Turnkey ASIC solutions from design to packaged parts. The company combines strong front-end and backend design strengths with close partnerships across the EDA, IP, and foundry ecosystem to reduce redesign risks and costs. Tessolve actively invests in R&D centers of excellence in areas such as 5G, mmWave, silicon photonics, HSIO, HBM/HPI, and system-level test, while also offering end-to-end embedded product design services for avionics, automotive, industrial, and medical applications. Serving Tier 1 clients, leading semiconductor companies, start-ups, and government entities, Tessolve has a broad global footprint across North America, Asia, and Europe, with multiple offices and test labs worldwide.
Role Description The Input Output Layout Engineer role at Tessolve is a full-time, on-site position based in Bengaluru South. The engineer will be responsible for developing and optimizing I/O layout designs, collaborating closely with circuit design teams to translate specifications into robust physical implementations. Day-to-day activities include creating and reviewing analog and mixed-signal layouts, performing layout-versus-schematic checks, and ensuring adherence to foundry design rules and internal quality standards. The role involves executing physical verification flows, identifying and resolving DRC/LVS issues, and contributing to layout best practices for performance, reliability, and manufacturability. The engineer will work in cross-functional teams, participate in design reviews, and support tape-out activities while maintaining clear documentation and communicating project status to stakeholders.
Qualifications
- Candidates should possess strong skills in layout-related domains, including Layout Design and Physical Verification, with hands-on experience using industry-standard EDA tools.
- Candidates should possess solid circuit-focused skills, such as Circuit Design, Analog, and Analog Circuits, with a good understanding of device behavior, matching, and parasitic effects.
- Relevant experience in I/O, analog, or mixed-signal layout for ASICs or SoCs, ideally on advanced process nodes.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field, or equivalent practical experience.
- Ability to interpret design schematics and constraints, and collaborate effectively with design, verification, and test teams.
- Familiarity with foundry process design kits (PDKs), DRC/LVS methodologies, and tape-out procedures.
- Strong attention to detail, problem-solving skills, and the
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