SiMaxTech Pvt Ltd
Website:
si-maxtech.com
Job details:
Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions for global customers. The organization offers strong capabilities across the semiconductor design spectrum, including analog circuit design, custom layout, physical design, RTL design, verification, and embedded design. With experience spanning mature nodes such as 28nm, 40nm, 65nm and above, as well as advanced nodes including 7nm, 5nm, 3nm, 2nm and 18A, SiMaxTech supports customers throughout the full chip development lifecycle. Guided by a vision to be a preferred design services partner, the company focuses on performance, quality, reliability, and scalability through continuous learning, innovation, and execution excellence. Applicants can expect a skilled engineering environment with opportunities to work on next-generation semiconductor products.
Role Description The Lead Analog Layout Engineer is a full-time, on-site role based in Bengaluru South. This role is responsible for leading analog and mixed-signal layout design for complex integrated circuits, collaborating closely with circuit designers to translate schematics into robust physical implementations. Day-to-day responsibilities include creating and optimizing transistor-level and block-level layouts, ensuring adherence to design rules, matching requirements, and performance targets across various technology nodes. The role involves driving physical verification closure (DRC, LVS, ERC, and related checks), resolving layout-related issues, and coordinating with cross-functional teams to meet project schedules and quality standards. The Lead Analog Layout Engineer will also mentor junior layout engineers, contribute to layout methodologies and best practices, and participate in design reviews to ensure scalable and high-quality layout solutions.
Analog Layout Engineer,
Experience : 4 - 12 Years
Location: Bangalore
Notice period: Immediate to 30 Days
Qualifications
- Candidates should possess strong skills in Layout Design and Custom Layout for analog and mixed-signal ICs.
- Candidates should possess solid skills in Analog, Analog Circuits, and Circuit Design, with an understanding of device physics and matching techniques.
- Candidates should possess expertise in Physical Verification, including DRC, LVS, ERC, and related sign-off flows.
- Candidates should possess proficiency with industry-standard EDA tools for analog layout and verification (e.g., Cadence Virtuoso, Mentor/Siemens, Synopsys).
- Candidates should possess experience working across multiple process technologies, preferably from 28nm down to advanced nodes, with awareness of layout constraints for high-performance designs.
- Candidates should possess good analytical and problem-solving abilities, attention to detail, and the capability to lead and mentor layout teams.
- Candidates should possess effective communication and collaboration skills for working with circuit, verification, and physical design teams.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, with several years of relevant analog layout experience in the semiconductor industry.
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