Website:
corpmatch.in
Job details:
Company Description Corp Match Private Limited (Corpmatch) is a placement-focused training and hiring ecosystem dedicated to transforming students into industry-ready professionals. The organization collaborates with colleges and companies to bridge the gap between academic learning and corporate expectations through structured, outcome-oriented programs. Corpmatch delivers IT and non-IT skill development, financial domain specialization, corporate readiness and interview preparation, campus hiring partnerships, and industry-aligned certification programs. By aligning its programs with real industry requirements and practical exposure, Corpmatch supports institutions in enhancing placement success, companies in accessing trained talent, and students in accelerating career growth. Its mission is to reduce the skill gap, improve employability, and create meaningful career opportunities across India.
Role Description The Physical Design Engineer will work full time on-site at Corpmatch’s Bengaluru South location, contributing to VLSI and ASIC design projects for partner organizations and training initiatives. Day-to-day responsibilities include floorplanning, place-and-route, clock tree synthesis, static timing analysis, and design closure, ensuring designs meet performance, power, and area targets. The role involves collaborating with front-end design teams to interpret constraints, integrating IPs, running physical verification (DRC, LVS), and debugging implementation issues. The engineer will prepare documentation, participate in design reviews, and provide technical input for training content and mentoring of learners where needed. This role requires close coordination with internal stakeholders and external partners to deliver reliable, production-ready physical design solutions.
Qualifications
- Candidates should possess strong skills in physical design flows, including floorplanning, place-and-route, clock tree synthesis, and timing closure.
- Candidates should possess skills in static timing analysis, signal integrity, power optimization, and design-for-manufacturability techniques.
- Candidates should possess skills in using industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor) for physical implementation and verification.
- Candidates should possess skills in collaborating with RTL and verification teams, interpreting design constraints, and resolving integration issues.
- Candidates should possess skills in documentation, problem-solving, and clear technical communication with cross-functional stakeholders.
- Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
- Experience in ASIC or SoC physical design projects, internships, or academic tape-outs is highly beneficial.
- Ability to work on-site in Bengaluru South, manage project timelines, and adapt to a fast-paced, training-focused ecosystem.
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