Technogen India Pvt. Ltd.
Website:
technogenindia.com
Job details:
- 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization.
- Proficient in writing clear, implementable micro-architecture specifications.
- Expertise in writing efficient RTL code in Verilog and SoC integration
- Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure.
- Should have worked on interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.
- Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce.
- Fluency with scripting languages (e.g., Perl, Python);
- Must have gone through at least one tapeout.
- Preferred: Silicon bring-up and debug experience
Experience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA
Click on Apply to know more.