Technogen India Pvt. Ltd.
Website:
technogenindia.com
Job details:
ASIC Design Engineer
Location: Hyderabad
Experience: 8+ Years
Notice Period: Immediate to 15 Days Preferred
Job Summary
We are looking for an experienced ASIC Design Engineer with strong expertise in RTL Design, SoC Integration, FPGA Validation, and Silicon Design. The ideal candidate should have hands-on experience in the complete SoC design lifecycle, RTL development, verification, synthesis, timing closure, and tape-out activities.
Key Responsibilities
- Design and develop RTL using Verilog/SystemVerilog.
- Perform SoC integration, verification, debugging, synthesis, and timing closure.
- Prepare and review micro-architecture specifications.
- Work on FPGA-based emulation platforms such as HAPS, Veloce, Cadence Protium, or Palladium.
- Perform RTL validation, assertions, coverage analysis, and design optimization.
- Collaborate with cross-functional teams throughout the ASIC development lifecycle.
- Support silicon bring-up, debugging, and production activities.
Required Skills
- 8+ years of experience in ASIC/SoC Design.
- Strong expertise in RTL Design and RTL Coding.
- Hands-on experience with Verilog, SystemVerilog, or VHDL.
- Experience in SoC Integration, RTL Verification, Synthesis, and Timing Closure.
- Experience with at least one complete ASIC Tape-out.
- Hands-on experience with FPGA validation (HAPS, Veloce, Cadence Protium, or Palladium).
- Strong scripting skills in Python or Perl.
- Experience with Bitbucket, Jenkins, and JIRA.
Protocol Experience (Any Four Mandatory)
- PCIe
- USB
- Ethernet
- DDR3/DDR4
- LPDDR
- I2C/I3C
- SPI
- SD/SDIO/eMMC
- UART
If you're interested in this opportunity, share your updated resume at rajeshwar.k@technogenindia.com.
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