Astera Labs
Website:
asteralabs.com
Company:
https://www.linkedin.com/company/astera-labs
Seniority: Not Applicable
Industries: Semiconductor Manufacturing
Job details:
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Position Overview
Job Description – IP Design Director
We are seeking an experienced and highly motivated IP Design Director to lead the architecture, design, development, and delivery of reusable Intellectual Property (IP) blocks for next-generation semiconductor products. This role combines deep technical expertise with strong people leadership and program management skills.
The successful candidate will be responsible for managing a team of IP design engineers while driving the successful execution of complex IP development programs. The role requires close collaboration with Architecture, Verification, Physical Design, DFT, Firmware, Software, Product Engineering, and SoC Integration teams to ensure delivery of high-quality IPs that meet performance, power, area, quality, and schedule objectives.
This position offers the opportunity to influence product roadmaps, establish engineering best practices, and contribute to the development of industry-leading semiconductor solutions.
Key Roles & Responsibilities
Technical Leadership
- Lead the end-to-end development of digital and mixed-signal IPs from architecture through silicon validation.
- Partner with architects and product teams to define IP requirements, features, performance targets, and scalability needs.
- Drive microarchitecture development and ensure alignment with overall SoC and product requirements.
- Review and approve architecture specifications, design documents, RTL implementations, and verification plans.
- Ensure IP designs achieve performance, power, area (PPA), reliability, and quality targets.
- Lead technical reviews and provide guidance on complex design challenges.
- Drive design trade-off decisions and risk mitigation strategies.
IP Development & Delivery
- Own the successful delivery of IP releases according to committed schedules and quality goals.
- Ensure all IP deliverables, including RTL, verification collateral, documentation, synthesis constraints, and integration guides, are completed and released on time.
- Drive IP reuse strategies to maximize engineering efficiency across multiple products and platforms.
- Establish standards for IP packaging, version control, configuration management, and release processes.
- Ensure compliance with internal design methodologies and industry best practices.
Team Leadership & People Management
- Build, lead, and mentor a high-performing IP design team.
- Set clear goals and expectations for team members.
- Conduct performance reviews, development planning, and regular coaching sessions.
- Identify skill gaps and implement training and development initiatives.
- Participate in workforce planning, recruiting, interviewing, hiring, and onboarding activities.
- Foster an inclusive, collaborative, and innovation-driven culture.
- Promote technical excellence and continuous learning within the organization.
Program & Project Management
- Define project execution plans, schedules, resource requirements, and development milestones.
- Monitor project progress and ensure alignment with business objectives.
- Track key performance indicators and project health metrics.
- Proactively identify technical, schedule, and resource risks and develop mitigation plans.
- Manage dependencies across multiple engineering functions.
- Provide regular status updates to senior management and stakeholders.
Cross-Functional Collaboration
- Collaborate closely with Architecture teams to define product requirements and implementation strategies.
- Work with Verification teams to ensure comprehensive verification planning, coverage closure, and quality metrics.
- Partner with Physical Design teams to achieve timing, power, and area objectives.
- Coordinate with DFT teams to implement robust testability features.
- Support Firmware and Software teams during bring-up and product development.
- Work with SoC Integration teams to ensure seamless integration of IPs into complex SoCs.
- Collaborate with Product Engineering and Silicon Validation teams during post-silicon activities.
Design Quality & Process Excellence
- Establish and enforce design methodologies, coding standards, and review processes.
- Drive continuous improvement initiatives focused on quality, productivity, and predictability.
- Implement best practices for:
- RTL design
- Lint and CDC/RDC closure
- Low-power implementation
- Design reviews
- Configuration management
- Design sign-off processes
- Champion root-cause analysis and corrective actions for design issues.
- Define and track quality metrics across IP development programs.
Silicon Bring-Up & Customer Support
- Support first-silicon bring-up and validation activities.
- Lead debugging and resolution of silicon issues related to owned IPs.
- Analyze post-silicon performance and reliability data.
- Drive corrective actions and future design improvements.
- Support internal and external customers with technical issue resolution when required.
Required Qualifications
Education
- Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field.
- Master's degree preferred.
Experience
- 18+ years of experience in semiconductor design and development.
- 5+ years of experience managing engineering teams and complex IP development programs.
- Proven track record of successfully delivering multiple IPs into production silicon.
- Experience managing cross-functional engineering programs across geographically distributed teams.
Technical Skills
Design Expertise
- Strong expertise in RTL design using Verilog/System Verilog.
- Deep understanding of digital design fundamentals.
- Experience with high-performance and low-power design techniques.
- Strong understanding of clocking, reset architecture, power management, and performance optimization.
IP Development Experience
Experience with one or more of the following:
- Processor and CPU subsystems
- AI/ML accelerator IPs
- DSP IPs
- Security and cryptographic IPs
- Interconnect and NoC architectures
- Memory controllers
- Cache subsystems
- PCIe/CXL controllers
- Ethernet and networking IPs
- USB controllers
- Storage IPs
- Multimedia and display IPs
SoC Development Knowledge
- Strong understanding of SoC architecture and integration.
- Experience with industry-standard protocols including:
- AXI
- AHB
- APB
- PCIe
- CXL
- USB
- Ethernet
- DDR/LPDDR
- Knowledge of ASIC development flows from RTL through tape-out.
Tools & Methodologies
Experience With
- Lint and CDC/RDC tools
- Synthesis flows
- Formal verification methodologies
- Low-power design flows (UPF/CPF)
- RTL simulation and debugging
- Version control systems
- Continuous integration methodologies
- Scripting languages such as Python, Perl, Tcl, or Shell
Preferred Qualifications
- Experience delivering IPs for AI, networking, datacenter, automotive, mobile, or high-performance computing products.
- Experience leading global engineering teams.
- Experience managing multiple concurrent IP development programs.
- Familiarity with safety-critical and security-focused design methodologies.
- Experience driving IP reuse strategies across multiple product generations.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Click on Apply to know more.
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