- Salary
- ₹10 - 20 LPA
- Experience
- 4+ yrs
- Location
- Bengaluru
- Job type
- Full-time
Required skills
- "Io design"
- "system verilog"
- "verilog"
Nice to have
- "pad ring"
- "bump map"
- "bump patern"
About the role
Job Title: Senior IO Design Engineer
Location: IDC, Bangalore
Key Responsibilities:
- Design planning of pad rings and package substrates, bump pattern construction.
- Dynamically define and optimize pad ring connectivity.
- Work with CFTs (Cross-Functional Team) on the deliverables (DEF, Verilog netlist etc.,)
- Interface with and support Architect, PD, PE, technology development and foundries teams.
- Support Verification, Emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds.
Required Qualifications:
- Minimum 4 years hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.
- Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL).
- Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent); specific tool experience is valuable but not mandatory.
- Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand-off).
- Experience with Verilog/System Verilog is required.
- Scripting experience or knowledge is a plus.
- Excellent analytical, communication (written and verbal), and documentation skills.
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