Senior Design Verification Engineer
Ciliconchip
- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
Required skills
- Python
- ethernet
- Perl
- TCL
- PCIe
About the role
Website:
ciliconchip.ai
Job details:
Key Requirements:
- Methodologies: Strong hands-on UVM / OVM and SystemVerilog (Constrained-Random Verification)
- Assertions & Coverage: SystemVerilog Assertions (SVA) & Functional Coverage modeling
- Protocols (Any): PCIe, USB, DDR, or Ethernet
- EDA Tools: Xcelium, VCS, or Questa
- Debug Tools: Verdi or SimVision
- Scripting: Python, Perl, or TCL
What You'll Do:
- Lead IP/subsystem verification, build UVM environments (monitors, scoreboards, drivers), track coverage closure, run regressions, and mentor junior engineers.
Click on Apply to know more.
This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.
