Website:
bestnanotech.in
Job details:
Senior Design Verification Engineer SoC Verification
Location: Bengaluru
Work Mode: On-site
Experience: 4.5+ years of relevant experience in SoC / Design Verification
Role Overview
We are looking for a Senior Design Verification Engineer with hands-on experience in SoC verification, SystemVerilog, assertions, coverage, and protocol verification. The role involves developing and executing verification strategies for complex SoCs integrating low-speed peripherals, high-speed interfaces, memory protocols, and third-party VIPs. The engineer will work across verification planning, testbench development, debugging, coverage closure, and sign-off.
Key Responsibilities
- Manage and execute SoC Design Verification activities for complex semiconductor projects.
- Develop comprehensive verification strategies, verification plans, and test plans based on design specifications.
- Develop, enhance, and maintain SystemVerilog-based verification environments and testbenches.
- Verify low-speed peripheral interfaces including I2C/I3C, SPI, UART, GPIO, and QSPI.
- Perform verification of high-speed protocols such as PCIe, Ethernet, CXL, MIPI, DDR, and HBM, based on project requirements.
- Develop and implement SystemVerilog Assertions (SVA) for protocol and functional checking.
- Drive functional coverage, code coverage, and toggle coverage analysis and closure.
- Debug simulation failures and identify issues across RTL, testbench, VIP, and SoC integration.
- Integrate and configure third-party Verification IP (VIP) from Synopsys and Cadence.
- Work with simulation and verification tools including Synopsys VCS and relevant Cadence verification tools.
- Support Gate-Level Simulation (GLS), X-propagation (Xprop), and UPF-based power-aware verification where required.
- Collaborate with RTL design, architecture, firmware, and verification teams to achieve verification milestones and project schedules.
Required Qualifications
- B.E. / B.Tech / M.E. / M.Tech in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline.
- 4.5+ years of relevant hands-on experience in Design Verification / SoC Verification.
- Strong understanding of SoC architecture, verification methodology, simulation, debugging, and coverage closure.
- Hands-on experience with SystemVerilog and assertion-based verification.
- Experience verifying SoCs containing multiple peripheral and high-speed interfaces.
- Experience working with industry-standard EDA verification and simulation tools.
Technical Skills
Verification Languages & Methodology
- SystemVerilog
- SystemVerilog Assertions (SVA)
- Constrained-random verification
- Coverage-driven verification
- SoC verification methodology
Low-Speed Protocols
High-Speed & Memory Protocols
- PCIe
- Ethernet
- CXL
- MIPI
- DDR
- HBM
Coverage & Debug
- Functional Coverage
- Code Coverage
- Toggle Coverage
- Simulation Debug
- Coverage Analysis and Closure
EDA Tools & VIP
- Synopsys VCS
- Cadence Verification Tools
- Synopsys VIP
- Cadence VIP
- Third-party VIP integration
Advanced Verification
- Gate-Level Simulation (GLS)
- X-propagation / Xprop
- UPF
- Power-Aware Verification
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