Globex Digital
Website:
globexdigitalcorp.com
Job details:
Company Description Globex Digital is a growing IT Services and Consulting organization, established in 2015 and actively engaged across software, semiconductor, AI, and GCC markets. The company specializes in staffing solutions, project-based hiring, and Recruitment Process Outsourcing (RPO), helping clients fill critical technical roles efficiently. As a Nasscom Certified Partner and Microsoft OEM Partner, Globex Digital combines strong industry credentials with deep domain expertise. Guided by a seasoned leadership team, the company focuses on connecting businesses with highly skilled professionals to support innovation and long-term growth.
Role Description The Physical Design Engineer will work on the implementation of complex digital designs from RTL to GDSII, including synthesis, floorplanning, place and route, and timing closure. Day-to-day responsibilities include collaborating with logic and RTL design teams, running physical verification checks, analyzing timing, power, and area, and driving sign-off across multiple tools and flows. The engineer will also contribute to design methodology improvements, documentation, and cross-functional reviews to ensure robust, scalable physical design solutions. This is a full-time, hybrid role based in California, United States, with a mix of on-site work and some work-from-home flexibility.
Qualifications
- Strong expertise in Physical Design flows, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
- 6+ Years experience in physical design
- Expert knowledge of the entire backend design flow (Synthesis, PnR, STA, Physical verification, LEC and EMIR )
- Expertise in latest technology nodes - 3nm, 5nm etc.
- Expertise in preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / PT ECOs
- Expertise in Physical verification at partition level, SS level and FC level.
- Experience in Formal verification / Logic Equivalence checks
- Experience in low power design implementation including UPF, multi-voltage domains, and power gating.
- Experience in EDA tools Fusion Compiler, EDI, DC Compiler, ICC2, Formality, Conformal LEC, Redhawk, StarRC and Prime time.
- Experience in scripting languages PERL TCL & Shell scripting .
- Prior experience on NVIDIA projects is must
Email to : rahul@globexdigitalcorp.com
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