We are looking for an experienced Design Verification Engineer – GLS to drive gate-level simulation and full-chip verification for complex SoC/ASIC designs.
Responsibilities
• Lead GLS and post-synthesis verification activities.
• Develop, execute and debug gate-level simulation environments.
• Work with SystemVerilog and UVM-based verification environments.
• Perform SDF-annotated timing simulations and analyze timing-related failures.
• Debug GLS failures across RTL, netlist, constraints, libraries and testbench environments.
• Collaborate with RTL, synthesis, STA, physical design and DFT teams to root-cause issues.
• Execute regression suites and track coverage and verification closure.
• Support full-chip and subsystem-level verification.
Requirements
• 2+ years of relevant Design Verification experience.
• Strong hands-on experience in Gate-Level Simulation (GLS).
• Strong SystemVerilog and UVM experience.
• Experience with SDF annotation and timing simulation.
• Strong debugging skills using industry-standard simulation/debug tools.
• Good understanding of digital design, RTL and SoC verification.
Good to have
• VCS / Xcelium / Questa
• Verdi / DVE
• UPF and low-power verification
• SVA, CDC and reset verification
• Python / Perl / Shell scripting
• Experience with full-chip SoC verification and post-silicon issues.
