Role and Responsibilities Responsible for developing testcases for SoC level verification scenarios.Execute Gate level simulations. Responsible for coverage closure
Skill Requirements:Hands on experience in SV/UVM based testbench development.Good understanding of system level scenarios in ARM based SoC.Basic knowledge in Bus protocols-APB,AHB,AXI Experience in debugging gate level simulations, low power simulations Good to have: Scripting knowledge in Python/Perl
Qualifications: B.Tech/B.E/M.Tech/M.E
