LeadSoc Technologies Pvt Ltd
Website:
leadsoc.com
Job details:
Lead Design Verification Engineer – PCIe / Ethernet
Location: Bengaluru
Experience: 6–12 Years
Role Overview
We are looking for a Lead Design Verification Engineer with strong hands-on expertise in SystemVerilog, UVM, PCIe and Ethernet to drive IP and SoC-level verification for complex, high-performance designs.
Key Responsibilities
- Lead IP and SoC-level verification for complex ASIC designs.
- Develop scalable SystemVerilog/UVM-based verification environments.
- Define verification strategy, test plans, coverage goals and sign-off criteria.
- Drive functional verification of PCIe and Ethernet interfaces/protocols.
- Develop constrained-random tests, sequences, scoreboards, monitors and functional coverage.
- Debug complex simulation failures using VCS/Verdi or equivalent tools.
- Drive functional and code coverage closure and verification sign-off.
- Work closely with RTL, Architecture, Firmware, DFT and Physical Design teams.
- Develop reusable verification components and improve verification methodologies.
- Mentor junior engineers and provide technical leadership.
Required Skills
- 6–12 years of ASIC/SoC Design Verification experience.
- Strong hands-on expertise in SystemVerilog and UVM.
- Strong experience in PCIe and Ethernet protocol verification.
- Experience with IP, subsystem and SoC-level verification.
- Good understanding of high-speed protocols, SoC architecture and IP integration.
- Experience with VCS/Verdi, assertions and functional coverage.
- Strong debugging and scripting skills using Python/Perl/Tcl.
- Experience in verification planning, regression and sign-off.
- Strong communication and technical leadership skills.
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