DV Engineer – Gate Level Simulation (BB45FT RM 4354)
Source-Right
- Location
- Hyderabad, Telangana, India
- Job type
- Full-time
About the role
Source-Right
Website:
source-right.com
Job details:
Position: DV Engineer – Gate Level Simulation (BB45FT RM 4354)
Key Skills
- Hands-on experience in Design Verification (DV) with Gate Level Simulation.
- Strong knowledge of SPICE, Verilog, SDF back-annotation, STA, and timing analysis.
- Experience with netlist simulation, timing libraries, timing arcs, and latch-based designs.
- Debug SDF annotation and gate-level simulation failures with root-cause analysis at gate/transistor level.
- Experience in SPICE-to-gate-level correlation and what-if analysis.
- Hands-on knowledge of SystemVerilog Assertions (SVA); UVM is a plus.
- Strong debugging, analytical, and communication skills.
Click on Apply to know more.
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