AIonSi
Website:
aionsi.com
Job details:
Company Description AIonSi is a semiconductor solutions startup delivering VLSI design and verification, automotive functional safety, and artificial intelligence services to clients worldwide. Led by seven industry experts, the company focuses on providing end-to-end solutions for complex SoC designs and taking full ownership from concept to implementation. AIonSi is positioned as a one-stop platform, emphasizing best-in-class service and uncompromising quality. The team offers comprehensive expertise in IP and SoC design, integration, verification, gate-level simulation (GLS), and physical design, providing opportunities to work on cutting-edge semiconductor projects.
Role Description This is a full-time, on-site Analog Layout Engineer position located in Bengaluru South, with opportunities for assignments related to Malaysia as needed. The role involves designing and implementing analog layout for complex circuits, including floorplanning, placement, routing, matching, and optimization for performance, area, and reliability. The engineer will collaborate closely with analog circuit designers to translate schematics into robust layouts, perform layout versus schematic (LVS) and design rule checks (DRC), and address physical verification issues. Day-to-day responsibilities include reviewing design specifications, preparing layout documentation, participating in design reviews, and coordinating with cross-functional teams to ensure tape-out quality and schedule adherence. The role also includes continuous improvement of layout methodologies, adherence to process design kits (PDKs), and support for design migration across technology nodes.
Qualifications
- Strong proficiency in layout design, including transistor-level layout, floorplanning, and routing for analog and mixed-signal blocks.
- Solid understanding of circuit design concepts with hands-on experience in analog and analog circuits for IP and SoC applications.
- Experience with physical verification, including DRC, LVS, ERC, and resolving sign-off issues in advanced process nodes.
- 3+ years of relevant industry experience as an Analog Layout Engineer or in a closely related role.
- Hands-on knowledge of industry-standard EDA tools (e.g., Cadence Virtuoso, Mentor/Siemens, Synopsys tools) and PDK usage.
- Familiarity with reliability and manufacturability considerations such as ESD structures, matching, guard rings, and latch-up prevention.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, or equivalent practical experience.
- Ability to work collaboratively in cross-functional teams, with strong communication, documentation, and problem-solving skills.
- Experience with high-volume product designs, SoC integration, or automotive/functional safety domains is an advantage.
Experience: 3+ Years
Location: Malaysia / Bangalore
Preference: Immediate joiners
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