Seminovaa
Company:
https://www.linkedin.com/company/seminovaa
Seniority: Mid-Senior level
Industries: Semiconductor Manufacturing
Job details:
Company Description Seminovaa™ is a deep-tech semiconductor design services company focused on driving innovation in ASIC/SoC design and verification, physical implementation, and DFT for global semiconductor leaders. The company delivers high-performance, first-time-right silicon by combining strong technical expertise with a commitment to precision and value. Guided by a mission to empower innovation, Seminovaa helps clients accelerate time-to-market while maintaining high standards of quality and reliability. Its end-to-end services span ASIC/SoC design and verification, RTL to GDSII, DFT and STA, post-silicon validation and test engineering, as well as IP integration and custom silicon solutions. Professionals joining Seminovaa work in a technology-driven environment that encourages problem-solving, collaboration, and continuous learning.
Role Description The PD - Lead is a full-time, on-site role based in Bengaluru, responsible for leading physical design activities for complex ASIC/SoC projects. This role includes planning and executing floorplanning, place-and-route, clock tree synthesis, static timing analysis, and physical verification, ensuring designs meet performance, power, and area targets. The PD - Lead will coordinate with front-end design, DFT, verification, and test engineering teams to drive end-to-end implementation and resolve design and timing issues. Daily responsibilities include reviewing design constraints, optimizing implementation flows, tracking project deliverables, mentoring team members, and preparing technical documentation and status reports. The role also involves collaborating with customers and internal stakeholders to align on specifications, schedules, and quality expectations.
Qualifications
- Candidates should possess strong physical design skills, including experience with floorplanning, place-and-route, clock tree synthesis, and layout optimization for ASIC/SoC.
- Candidates should possess expertise in timing analysis and sign-off, including static timing analysis (STA), power and signal integrity analysis, and timing closure methodologies.
- Candidates should possess familiarity with industry-standard EDA tools and flows for physical implementation and verification (e.g., tools for P&R, STA, DRC/LVS, EM/IR analysis).
- Candidates should possess knowledge of front-end design concepts such as RTL design, synthesis, constraints management, as well as an understanding of DFT requirements.
- Candidates should possess strong leadership and collaboration skills, with experience guiding technical teams, coordinating with cross-functional stakeholders, and managing project timelines.
- Candidates should possess solid problem-solving and analytical skills, along with the ability to document design decisions and communicate complex technical topics clearly.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field is preferred; prior experience in semiconductor physical design leadership is highly beneficial.
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