HrdWyr
Website:
hrdwyr.com
Company:
https://www.linkedin.com/company/hrdwyr
Seniority: Not Applicable
Industries: Semiconductor Manufacturing
Job details:
Job Description:
- Responsible for chip level STA convergence from early stages to signoff.
- Participate in top level floor plan and clock planning.
- IP & SoC timing constraints definition for all modes including DFT
- Constraints quality check
- Multimode-multi corner timing analysis.
- Timing ECO generation.
- Block and SoC level timing convergence.
- Block and SoC level Synthesis.
- Block and SoC level equivalence check.
Experience Required:
- 5 to 8 years of experience in SOC level timing convergence
- Synthesis and equivalence check
- Strong timing concepts
- Working knowledge of low power design involving multiple power domains.
- Proficiency in scripting languages such as TCL, Perl, or Python for automation.
- Familiarity with industry-standard EDA tools for STA like Tempus and PrimeTime
- Exposure to complex design having multiple asynchronous clocks.
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