EnCharge AI
Website:
enchargeai.com
Company:
https://www.linkedin.com/company/encharge-ai
Seniority: Mid-Senior level
Industries: Semiconductor Manufacturing, Computer Hardware Manufacturing, and Software Development
Job details:
Principal DFT Engineer -14-20years
(www.enchargeai.com
)
Location: Greater Bengaluru Area (Hybrid)/Remo
te
About Compa
ny:EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI syste
ms.
Principal DFT Engineer -14-20y
ears
Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environm
ents.
As the Design for Test (DFT) Architect, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deplo
yment.
Key Responsib
ilitiesArchitectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, and
MBIST.
Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data
centers.
Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Lo
gic BIST.
Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and pow
er impact.
Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize
test time.
Technical
RequirementsExperience: 14-20 years in DFT, with at least 2 years in a leadership or pri
ncipal role.
Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Ca
dence Modus).
Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities and boundary scan (I
EEE 1149.1/6).
Advanced Nodes: Proven track record with FinFET nodes (7nm,
5nm, or below).
Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for
edge e
fficien
cy.
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ContactUdaymuday
_bhaskar@yahoo.com
Mulya Technologies"Mining the Kn
owledge Community"
Click on Apply to know more.
