Design Verification Manager
Texas Instruments
- Experience
- 8+ yrs
- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
Required skills
- Perl
- Python
- UVM
- SystemVerilog
- Specman
- Cadence Xcelium
- Cadence vManager
- Cadence Formal
- Verilog
- VHDL
About the role
8+ years DV experience in IP/SS/SOC/post-silicon with Bachelor's or Master's in EE/ECE/CS; strong people management and project leadership; expertise in UVM/SystemVerilog, C-based verification, scripting, protocols, and Cadence tools; export control clearance required.
About Texas Instruments
Global semiconductor company designing and manufacturing analog and embedded processing chips.
This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.
