Mythic
Website:
mythic.ai
Job details:
Mythic is a fast-paced AI startup seeking passionate engineers who thrive in dynamic environments and embrace broad, flexible roles. We are looking for hands-on Physical Design (specifically STA and Synthesis) Engineers eager to pushboundaries in advanced technology nodes. As part of a unified team across geographies, you will drive innovation from guiding RTL teams to producing high-quality designs through to first-pass silicon success. With end-to-end ownership, you’ll tackle challenges in physical design with a focus on scalability, speed of execution, and efficiency, in a fast-moving AI hardware landscape with a strong emphasis on analog IP integration. We welcome talent across all experience levels—seasoned professionals as well as sharp, driven early-career engineers whose passion for deep learning and innovative solutions enables them to quickly contribute at a high level.
JD for Staff/Senior Staff STA Engineer
Responsibilities:
Participate in the development of Physical Design (PD) methodologies across the RTL-to-GDSII flow using industry-standard tool (Cadence) with focus on multi-corner, multi-mode Synthesis and STA for lower technology nodes like 7nm, 5nm.
- Perform lead level hands-on work in one or more areas including Synthesis, Formal Equivalence, Static Timing Analysis (STA) at both module and top level.
- Take full ownership of the STA process at the module level and provide support in top-level integration, collaborating closely with RTL designers, DFT teams, and fabrication partners.
- Provide technical mentorship, guiding team members and managing PD team interactions to ensure successful SoC implementation.
- Drive PPA optimization, including low-power clock tree design for high- performance systems, and achieve timing closure across multiple corners and use cases.
- Champion an automation-first approach, developing methodologies in TCL, PERL, or Python to significantly improve team efficiency.
Requirements:
- B.Tech/M.Tech/PhD in Electrical Engineering (EE) or Electronics & Communication Engineering (ECE).
- 6-10+ years of experience in the STA domain.
- Deep expertise in one or more areas (Synthesis, Formal Equivalence, STA,
including Timing signoff) with strong working knowledge of the entire STA
flow.
- Proven track record of successful tapeouts for multi-million gate, multi-
hierarchy designs at advanced nanometer technology nodes.
- Solid understanding and hands-on experience in calculating timing margins
due to reliability, DVFS, multi-voltage, power-gating, reducing signoff
timing corners, SDC validation leading to 1 st pass silicon success.
- Strong background in automation of STA methodologies using TCL, PERL,
or Python.
- Willingness to expand beyond core expertise, with a team-oriented, can-do
attitude and commitment to mastering the full RTL-to-GDSII flow.
Nice to Have Sills:
- Knowledge of chiplet-based design limitations and their impact on timing
closure.
- Experience in Sub-10nm designs
- Familiarity and hands-on experience with Cadence toolsets.
Click on Apply to know more.
