Ananant Systems Private Limited
Website:
ananantsys.com
Job details:
Job Title: SoC Verification Engineer
Hardware + Full Chip Verification | AI-Native DSP SoC
📍 Location: Noida, Uttar Pradesh (On-site)
🕒 Experience: 6–14 years
💼 Employment Type: Full-Time
About the Role
Ananant Systems is building a proprietary AI-native DSP SoC targeting next-generation applications across 5G/6G wireless, Edge AI inference, Vision AI, camera, video, and radar systems.
We are looking for a highly experienced SoC Verification Engineer to own end-to-end functional verification of the full chip — from IP integration and SoC validation to pre-silicon sign-off and post-silicon bring-up support.
This role demands deep expertise in full-chip verification, complex interface integration, and system-level validation in advanced semiconductor nodes.
Key Responsibilities
- Own and develop the SoC-level verification plan, coverage model, and traceability matrix.
- Build and maintain UVM-based SoC testbench (top-level environment, virtual sequencer, chip-level scoreboard, coverage).
- Integrate and verify high-speed interfaces: PCIe Gen3/4, USB3, JESD204B, MIPI CSI-2/DSI, DDR/LPDDR, AXI/AHB/APB.
- Drive end-to-end datapath verification for workloads including 5G/6G, AI inference, video/camera, radar, and Vision AI.
- Verify critical SoC components: DMA, Interrupt Controller, Clock/Reset, Power Management (UPF), DFT (Scan, MBIST, LBIST, JTAG).
- Own regression management, coverage closure, gate-level simulation (GLS with SDF), and tapeout sign-off.
- Collaborate cross-functionally with design, architecture, and physical design teams
- Support post-silicon bring-up, validation, and debug.
Required Skills & Expertise
Expert Level:
- UVM (SoC environment, virtual sequencer, chip-level scoreboard)
- SystemVerilog
- Regression management and scripting (Python / Perl / Shell)
Advanced Level:
- Peripheral VIP integration (PCIe, USB3, JESD204B, MIPI, DDR)
- Low-power verification (UPF)
- Clock/reset verification
- DFT simulation and validation
- End-to-end datapath verification methodologies
Tools & Domain:
- Hands-on experience with VCS, Xcelium, or Questa
- Strong debugging skills using waveform analysis tools
- Solid understanding of wireless, AI, or multimedia SoCs
Mandatory Experience
- Named contributor on at least 2 commercial SoC tapeouts (16nm or below) with full-chip verification exposure
- Ownership of at least one major verification domain (e.g., IO/peripherals, power management, or datapath) through tapeout
- Experience in post-silicon bring-up and debug is highly preferred
Why Join Ananant Systems
- Work on a cutting-edge AI-native DSP SoC powering multiple high-impact domains
- End-to-end exposure from architecture → verification → silicon → system
- High ownership and opportunity to influence next-gen semiconductor products
- Competitive compensation + ESOPs in a fast-growing deep-tech startup
- Opportunity to work on advanced FinFET technology nodes
Click on Apply to know more.
