Tessolve
Website:
tessolve.com
Job details:
Job Description – Design Verification Engineer
Job Title: Design Verification Engineer – RISC-V & DDR
Location: Bengaluru
Experience: 5+ Years
Notice Period: Immediate to 30 Days
Role Overview
We are looking for an experienced Design Verification Engineer with strong hands-on expertise in RISC-V and DDR verification to work on complex IP/SoC verification projects.
Key Responsibilities
- Develop and execute comprehensive Design Verification Plans, test plans, test cases, and verification strategies.
- Develop and maintain SystemVerilog/UVM-based verification environments.
- Perform functional verification of RISC-V-based designs/IPs.
- Verify DDR interfaces/controllers and related memory subsystems.
- Develop UVM sequences, drivers, monitors, scoreboards, checkers, assertions, and coverage models.
- Perform functional and code coverage analysis and drive coverage closure.
- Debug RTL, testbench, and simulation failures and perform detailed root-cause analysis.
- Work closely with Design, Architecture, Firmware, and SoC teams to identify and resolve issues.
- Execute regressions and analyze failures to ensure verification quality and completeness.
- Contribute to verification methodology improvements and development of reusable verification components.
Required Skills
- Strong hands-on experience in SystemVerilog and UVM.
- Good understanding of RISC-V architecture and processor-based SoC verification.
- Hands-on experience in DDR / DDR controller verification.
- Experience in developing UVM testbenches from scratch.
- Strong knowledge of:
- Verification planning and test-plan development
- UVM testbench architecture
- Test and sequence development
- Assertions / SVA
- Functional and code coverage
- Regression and debug
- Strong debugging and problem-solving skills.
- Experience with simulation/debug tools such as Questa, VCS, Verdi, or equivalent.
- Scripting knowledge in Python, Perl, or Shell is an added advantage.
Good to Have
- Experience with RISC-V cores, buses, and SoC interconnects.
- Experience with DDR4 / DDR5 or other high-speed memory interfaces.
- Knowledge of AMBA protocols such as AXI/AHB/APB.
- Experience with PCIe, Ethernet, or other high-speed interfaces is an added advantage.
- Exposure to emulation/FPGA or post-silicon validation is a plus.
Candidate Profile
- Strong analytical, debugging, and problem-solving skills.
- Ability to independently own verification activities from test planning through coverage closure.
- Good communication and cross-functional collaboration skills.
- Ability to work effectively in a fast-paced semiconductor development environment.
Apply Now
📍 Location: Bengaluru
💼 Experience: 5+ Years
⏳ Notice Period: Immediate to 30 Days
📩 Interested candidates can share their updated CV at:
manjula.patil@tessolve.com
Click on Apply to know more.
