"senior DFT engineer" "Lead dft engineer"

SiSoC Semiconductor Technologies Pvt Ltd.

Required skills

ATPG – Pattern generation, ATPG netlist and timing sims, ATPG Coverage analysis and improvement

Tools – Tessent TestKompress ATPG or Synopsys Tetramax

with experience in MBIST pattern generation, simulations, and post-silicon pattern debug analysis working with Test engineers

with experience in MBIST pattern generation, simulations, and post-silicon pattern issue recreation in sims.

Tools flow: Synopsys SMS, Yield Accelerator

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