Sykatiya Technologies Pvt Ltd
Website:
sykatiya.com
Job details:
Description: Lead / Staff/Sr. Staff Physical Design Engineer
Experience: 10+ Years Location: Bangalore
About the Role
We are looking for a high-performing Techno-Functional Lead / Staff/Sr.Staff Physical Design Engineer with 10+ years of experience in leading complex, multi-million gate ASIC/SoC physical design projects. In this hybrid role, you will act as a primary technical authority on physical implementation while simultaneously steering execution strategy, resource allocation, risk mitigation, and stakeholder engagement. You will bridge the gap between technical execution and business delivery, ensuring complex chips tape out on time with optimal Power, Performance, and Area (PPA).
Responsibilities Technical Leadership
• RTL-to-GDSII Execution: Directly own and participate in the full physical design flow including floorplanning,
power grid design, placement, CTS (Clock Tree Synthesis), routing, signal integrity (IR drop / EM), STA (Static Timing Analysis), and physical verification (DRC/LVS).
• SoC-Level Physical Design: Own physical implementation and closure activities for complex SoC designs, including integration of high-speed and complex IP blocks.
• SerDes IP Integration & Implementation: Work hands-on with SerDes IPs at the SoC level, including physical integration, floorplan considerations, timing, congestion, signal integrity, routing, and implementation-related issue resolution.
• Timing & PPA Closure: Drive setup/hold timing closure, congestion optimization, signal integrity analysis, and Power, Performance, and Area (PPA) optimization.
• Architecture & Methodology: Define physical implementation methodologies and custom automation scripts (Tcl/Python) tailored for ultra-low power and high-speed design constraints.
• Advanced Technology Nodes: Drive design closure on sub-7nm process nodes (e.g., 5nm, 3nm, 2nm) dealing with multi-patterning, high-density cell placement, complex power domain management (UPF/CPF), and thermal considerations.
• Cross-Functional Collaboration: Partner with Architecture, DFT, Physical Verification, Synthesis, STA, RTL, and Verification teams to resolve complex timing, floorplan, routability, and implementation bottlenecks early in the execution cycle.
Functional & Project Management
• Technical Ownership & Project Planning: Serve as the technical owner for complex sub-systems or full-chip SoC designs; define schedules, key execution milestones, tape-out roadmaps, and delivery metrics.
• Team Leadership & Mentorship: Lead, guide, and mentor a team of physical design engineers. Conduct technical design reviews and establish standard operational procedures while continuing to contribute hands-on to implementation.
• Risk & Issue Management: Proactively identify technical, tool, or resource bottlenecks, formulate mitigation strategies, and drive decision-making processes under high pressure.
• Stakeholder & Vendor Alignment: Interface with key internal/external stakeholders, foundry partners, and EDA vendors (Synopsys, Cadence) to evaluate tools, manage software licensing needs, and resolve design enablement issues.
Required Qualifications
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication Engineering, Microelectronics, or a related field.
• Experience: 10+ years of hands-on Physical Design experience with a proven track record of successful tape-outs on advanced technology nodes (7nm and below).
• SoC-Level Physical Design: Strong and practical experience in complex SoC-level physical implementation from netlist to signoff.
• SerDes IP Experience: Hands-on experience with SerDes IPs is mandatory. The candidate must have practical exposure to SerDes-related physical implementation/integration challenges at the SoC level.
• Hands-On Requirement: Candidate must be willing to remain actively hands-on with Physical Design implementation activities.
• EDA Tool Proficiency: Advanced proficiency in standard EDA tool suites: Synopsys (Fusion Compiler, IC Compiler II (ICC2), PrimeTime, StarRC); Cadence (Innovus, Tempus, Voltus, Pegas); Siemens/Calibre (Calibre DRC/LVS/PERC).
• Scripting: Advanced skills in Tcl, Python, or Perl for automated flow development and productivity enhancements.
• Core Physical Design Skills: Strong experience in floorplanning, power planning, placement, CTS, routing, timing closure, congestion analysis, signal integrity, physical verification, and signoff.
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