We are looking for an experienced Senior RTL Design Engineer with strong expertise in ASIC/SoC RTL design and hands-on experience in CPU core or processor subsystem design.
The ideal candidate should have 6+ years of RTL design experience, including at least 2+ years working on CPU cores or processor subsystems, with strong knowledge of computer architecture, SystemVerilog/Verilog, AMBA protocols, RTL development, lint/CDC, synthesis, and scripting.
Key Responsibilities
- Design and develop CPU core / processor subsystem RTL using SystemVerilog and Verilog.
- Work on CPU microarchitecture including pipelines, hazards, branch prediction, caches, MMU, and interrupt handling.
- Develop and integrate RTL for ASIC/SoC designs.
- Work with AMBA protocols, including AXI, AHB, and APB.
- Perform RTL quality checks including lint and CDC analysis.
- Support synthesis using Synopsys Design Compiler or Cadence Genus.
- Debug RTL issues and support simulation using Synopsys VCS or Cadence Xcelium.
- Develop automation scripts using Python, TCL, Perl, or Bash.
- Collaborate with architecture, verification, physical design, and SoC integration teams.
- Participate in RTL design reviews, debugging, optimization, and signoff activities.
