Website:
aerlync.com
Job details:
🚀 We're Hiring | Technical Lead – PCIe Design Verification (DV) | Ahmedabad
Are you passionate about ASIC/SoC Design Verification and ready to lead the verification of next-generation PCIe subsystems?
Aerlync Labs is looking for an experienced Technical Lead – Design Verification (PCIe) to join our growing semiconductor engineering team. If you have a strong background in SystemVerilog, UVM, PCIe protocols, and enjoy mentoring teams while solving complex verification challenges, we'd love to hear from you!
📍 Location: Ahmedabad, India (Hybrid/On-site)
💼 Experience: 5+ Years
What You'll Do
🔹 Lead the end-to-end Design Verification of PCIe IPs and SoC-level integration to ensure first-pass silicon success.
🔹 Architect and develop scalable, reusable SystemVerilog (SV) and UVM verification environments from scratch.
🔹 Define comprehensive verification strategies, test plans, and functional coverage models.
🔹 Drive regression execution, analyze failures, and debug complex protocol issues across PCIe transaction, data link, and physical layers.
🔹 Mentor and guide verification engineers through technical leadership and code reviews.
🔹 Collaborate closely with RTL designers, system architects, and emulation teams to accelerate product development.
Required Skills
✔ 5+ years of hands-on experience in ASIC/SoC Design Verification.
✔ Strong expertise in SystemVerilog (SV) and UVM methodologies.
✔ Proven experience building UVM testbenches, agents, scoreboards, and sequences from the ground up.
✔ Deep understanding of PCIe Gen4/Gen5/Gen6, including SR-IOV, AER, flow control, ordering rules, link training, and power management.
✔ Hands-on experience with industry-standard EDA tools such as VCS, Xcelium, or Questa, and waveform debugging using Verdi.
✔ Excellent debugging and analytical problem-solving skills.
Preferred Skills
⭐ Experience with hardware emulation platforms such as Palladium, Veloce, or ZeBu.
⭐ Proficiency in Python, Perl, or Bash scripting for regression automation.
⭐ Experience building or scaling a Design Verification team.
⭐ Familiarity with AI-assisted verification workflows and modern DV automation practices.
Why Join Aerlync Labs?
🌟 Work on cutting-edge semiconductor and high-speed interface technologies.
🌟 Take ownership of complex PCIe verification programs from architecture through tape-out.
🌟 Collaborate with a highly skilled engineering team in a fast-growing technology company.
🌟 Accelerate your career while building next-generation silicon solutions.
📩 Interested? We'd love to hear from you!
Send your resume to durai@aerlync.com or connect with us directly on LinkedIn.
Know someone who would be a great fit? Tag them in the comments or share this opportunity with your network!
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