KriSemi Design Technologies Pvt Ltd
Website:
krisemidesigntech.com
Job details:
Role Overview
We are seeking a highly motivated Mixed Signal / Custom IP Design Engineer with approximately 5 years of industry experience. The role focuses on transistor-level circuit design, advanced simulation, characterization, yield optimization, statistical validation, and automation of custom and mixed-signal IP development workflows. Candidates who effectively leverage AI tools to improve engineering productivity, debugging, automation, and design exploration will be highly preferred.
Qualification: M.Tech (VLSI / Microelectronics / ECE)
Experience: ~5 Years
Key Responsibilities
- Design and develop analog, mixed-signal, and custom IP blocks
- Perform transistor-level design, optimization, and validation
- Execute extensive simulation and verification across PVT corners
- Perform Monte Carlo, mismatch, sensitivity, and yield analysis
- Automate simulation, characterization, regression, and reporting flows using TCL, Perl, and Python
- Characterize IP performance and ensure robustness against process variations
- Collaborate with layout, verification, product, and silicon teams
- Drive automation initiatives and improve productivity using scripting and AI tools
- Support silicon bring-up and post-silicon debug activities when required
Mandatory Technical Expertise
- Strong understanding of CMOS device physics, analog design fundamentals, simulation methodologies, statistical analysis, and IP characterization
- Hands-on experience with TCL, Perl, and Python for automation of simulation, characterization, regression, data extraction, and reporting workflows
- Familiarity with Linux/Unix environments and shell scripting
Key Skills Required
- Transistor-Level Circuit Design
- Cadence Virtuoso Design Environment
- DC, AC, Transient and Noise Simulations
- Monte Carlo Analysis & Statistical Validation
- PVT Corner Analysis and Design Robustness
- Yield, Mismatch and Variation Analysis
- Custom / Mixed-Signal IP Development
- Strong Debugging and Root-Cause Analysis Skills
- AI-assisted Engineering Productivity and Workflow Automation
Preferred Domain Experience
- Memory IPs (SRAM, NVM, NAND, Flash-related circuits)
- Data Converters (ADC/DAC)
- PLLs, Clocking Circuits and Timing IPs
- Power Management Circuits (LDOs, References, Regulators)
- High-Speed Interface or Mixed-Signal IP Development
Good to Have
- Understanding of custom layout practices and layout-dependent effects (LDE)
- Experience working closely with layout engineers
- Knowledge of reliability, ESD, EMIR, and variation-aware design methodologies
- Exposure to silicon validation and characterization
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