SEMI LEAF
Website:
semi-leaf.com
Job details:
ASIC RTL Design Engineer – RTL / UPF / Micro-architecture
· Experience: 8–12 Years
· Location: Bangalore
Must-Have Skills
- 8–12 years of experience in ASIC RTL Design.
- Strong hands-on experience in Verilog/SystemVerilog.
- Expertise in Micro-architecture development and RTL implementation.
- Hands-on experience with UPF (IEEE 1801) and low-power design methodologies.
- Strong understanding of the complete ASIC Design Flow (RTL → Verification → Synthesis → STA → Physical Design).
- Experience with Lint, CDC/RDC, Synthesis, STA, and RTL debug.
- Good knowledge of Power Domains, Isolation, Level Shifters, Retention, and Power State Tables (PST).
- Experience optimizing designs for Power, Performance, and Area (PPA).
- Familiarity with standard bus/protocols such as AXI, AHB, APB; exposure to PCIe, DDR, Ethernet, USB, or MIPI is a plus.
- Strong debugging, problem-solving, and cross-functional collaboration skills.
Key Responsibilities
- Own block-level RTL design from micro-architecture to RTL sign-off.
- Develop synthesizable RTL and implement UPF-based low-power intent.
- Collaborate with Architecture, DV, STA, Physical Design, and DFT teams.
- Support RTL verification, synthesis, timing closure, and power-aware implementation.
- Review RTL, micro-architecture, and UPF to ensure quality and compliance.
- Mentor junior engineers and drive technical discussions.
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