Chiplogic Technologies
Website:
chiplogictech.com
Job details:
Company Description Chiplogic Technologies (Chiplogic) is an IP and Product Engineering Services company founded in 2018, specializing in Semiconductor, Systems, IoT, and AI/ML domains. The organization focuses on delivering high-quality, dependable design and engineering services from concept to silicon for semiconductor solutions. Chiplogic provides Offshore Development Centers (ODC) and full turnkey design and system solutions, including proof-of-concept (POC) development. The company also offers IoT system solutions and AI/ML services built around its proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework, creating innovative video and real-time analytics applications. Team members can expect to work in a technology-driven environment with opportunities to contribute to advanced product and IP development.
Role Description We are looking for an experienced Design Verification Lead with 10+ years of hands-on experience in SoC verification, with strong expertise in LLC/Cache, high-bandwidth AXI-based NoC/Data Fabric, and Scheduler Subsystems. The candidate will lead verification activities from architecture understanding and test planning through execution, debug, coverage closure, and sign-off.
The role requires strong technical leadership and experience working closely with RTL Design, Architecture, Firmware, Performance, and SoC teams.
Key Responsibilities
- Lead end-to-end functional verification of complex SoC subsystems.
- Own verification strategy, planning, execution, coverage closure, and sign-off.
- Develop and review test plans, verification environments, testbenches, assertions, checkers, and coverage models.
- Drive verification of LLC/Cache subsystem, including cache coherency, transactions, replacement policies, cache states, and error scenarios.
- Verify SoC Data Fabric, with primary focus on high-bandwidth AXI-based NoC.
- Validate AXI transaction flows, bandwidth, ordering, arbitration, QoS, outstanding transactions, congestion, and corner cases.
- Verify Scheduler Subsystem, including RISC-V scheduler and firmware-driven flows.
- Work closely with firmware teams to validate hardware/firmware interaction and end-to-end use cases.
- Debug complex RTL, simulation, and system-level failures and drive issues to closure.
- Perform functional, code, assertion, and coverage analysis and drive coverage closure.
- Mentor and technically guide junior and senior verification engineers.
- Participate in architecture and design reviews and identify verification challenges early.
- Collaborate with cross-functional teams across Design, Architecture, Firmware, Performance, Emulation, and Validation.
- Drive verification quality, methodology improvements, and automation.
Required Technical Skills
- 10+ years of experience in ASIC/SoC Design Verification.
- Strong hands-on experience with SystemVerilog and UVM.
- Strong understanding of SoC architecture and verification methodologies.
- Excellent knowledge of AXI/AMBA protocols.
- Strong experience in NoC / Data Fabric verification, preferably high-bandwidth AXI-based interconnects.
- Experience with LLC / Cache verification and cache/coherency concepts.
- Experience with RISC-V architecture and verification.
- Exposure to firmware-driven verification and hardware/software interaction.
- Strong debugging skills using simulation and waveform/debug tools.
- Experience with functional coverage, code coverage, assertions, and coverage closure.
- Experience with industry-standard simulators such as VCS, Questa, Xcelium, or equivalent.
- Good scripting/programming skills in Python, C/C++, or Perl.
Preferred Skills
- Experience with CPU/SoC subsystems and cache coherency protocols.
- Knowledge of ACE/CHI or other coherent interconnect protocols.
- Experience with performance, stress, and bandwidth verification.
- Experience with formal verification is an advantage.
- Experience with emulation or FPGA-based verification is a plus.
- Prior experience leading verification teams or owning large verification projects.
Leadership Expectations
- Ability to independently own verification for a complex subsystem.
- Strong technical decision-making and problem-solving capabilities.
- Ability to mentor engineers and review verification methodologies.
- Excellent communication and stakeholder-management skills.
- Ability to work in a fast-paced, cross-functional semiconductor product development environment.
Click on Apply to know more.
