Role and Responsibilities Learn on SEC UVM. Understand Top DV builds for different flavors with power, netlist, GLS, RTL, and power net builds.Work closely with block DV, Top design, PI/PD, DFT teams to work on collaterals and make Top build as required Debug initial failures from C based test or SV based test cases Understand issue, raise defects, follow up fixes and create final top build Able to debug bus transaction issues and port level issues Integrate current workflow into AI enabled workflowSkill Requirements: Working knowledge on SV/UVM Working knowledge on (GPIO / AHB, ACE lite, ACP, AXI3, AXI4, APB)Working knowledge on Perl / Python Understanding of SOC boot flowUnderstanding and working knowledge on building UVM test benchesWorking knowledge / Understanding of simulator tools and waveform debugGood to have: AI enabled workflow knowledgeAI assist debug from cadence / SynopsysWorking knowledge on any Agentic AIExperience: Good to have: Qualifications: B.Tech/B.E/M.Tech/M.E