- Experience
- 2+ yrs
- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
Required skills
- Soc verification
- Design verification
- Verdi
About the role
Mandatory Skills
- 2–5 years of experience in Design Verification/IP Verification.
- Strong hands-on experience in SystemVerilog and UVM.
- Good understanding of AMBA protocols (AXI/AHB/APB).
- Experience in testbench development.
- Strong debugging and problem-solving skills.
- Knowledge of functional coverage, assertions (SVA), and constrained random verification.
- Experience with simulation tools such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim.
- Good understanding of RTL design concepts.
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