Developer (Front End Infrastructure CAD Engineer)
Ericsson
- Salary
- $178k - $194k
- Experience
- 5+ yrs
- Location
- Austin, Texas, United States
- Job type
- Full-time
Required skills
- Verilog
- SystemVerilog
- VHDL
- UVM
- SystemC
- Python
- Perl
- Bash
- csh
- tcl
- Red Hat Enterprise Linux
- SUSE Linux Enterprise Server
- Jenkins
About the role
Bachelor's in Electrical/Electronics Engineering or related field with 5 years experience, or Master's with 2 years; experience in ASIC/SoC/FPGA design using Verilog, SystemVerilog, VHDL, UVM, SystemC; scripting with Python, Perl, Bash, csh, tcl; Linux and Jenkins.
About Ericsson
Global provider of communications technology, software, and services.
This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.
