- Experience
- 6+ yrs
- Location
- Austin, Texas, United States
- Job type
- Full-time
Required skills
- SystemVerilog
- Verilog
- UVM
- Python
- Tcl
- Perl
- shell scripting
- Jenkins
- Git
- CI/CD
- AMBA
- PCIe
- DDR
- MIPI
- Ethernet
- SerDes
- SPI
- I2C
- UART
- JasperGold
- Synopsys VCS
- Verdi
- DVE
- SpyGlass
- Cadence Xcelium
- SimVision
- Mentor Questa
- ModelSim
- Riviera-PRO
- Vivado
- Intel Quartus
- Jira
- Confluence
- LabVIEW
About the role
Bachelor's or master's in electrical/computer engineering or related; 6+ years design verification experience; SystemVerilog, Verilog, UVM; scripting in Python/Tcl/Perl/shell; debugging RTL and gate-level simulations; knowledge of SoC architectures and interfaces.
About Ericsson
Global provider of communications technology, software, and services.
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