Design Verification Manager(DV)
Avicena Tech
- Experience
- 8+ yrs
- Location
- Sunnyvale, California, United States
- Job type
- Full-time
About the role
Bachelor's or Master's in Electrical/Computer Engineering; 8+ years ASIC/SoC verification experience including 2+ years managing engineers; expertise in SystemVerilog and UVM; proven track record of tape-out success.
About Avicena Tech
Privately held company developing microLED optical interconnects for chip-to-chip links in AI, high-performance computing, and memory systems.
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