Alp Consulting Ltd.
Website:
alp.consulting
Job details:
ASIC Front-end Design engineer (5-12 Years)
This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
What you'll do:
- We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills.
- You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies.
- Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards.
Responsibilities:
- Define and architect high-performance blocks for the latest, most advanced networking ASICs
- Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
- Collaborate with the verification team in the development of the testplan and assist in debugging test failures
- Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
What you need to bring:
- Strong Verilog RTL coding skills
- Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
- Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
- Knowledge of high performance memory subsystems
- Knowledge of multi-domain clock synchronization and high-speed serial interfaces
- Strong problem solving and ASIC debugging skills
- Excellent written and verbal communications skills
- MSEE or BSEE is required
- experience range 5-12 years
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Click on Apply to know more.