Dexcel Electronics Designs Pvt. Ltd
Website:
dexceldesigns.com
Job details:
🚀 Hiring AMS & DMS Engineers | Bangalore | On-site | Direct Product Client
We are hiring Analog Mixed-Signal (AMS) and Digital Mixed-Signal (DMS) Engineers with 5+ years of experience for a leading direct product client in Bangalore.
1. Analog Mixed Signal with Spice:
Key Responsibilities
- Perform AMS/SPICE simulations at IP, subsystem, and full-chip/SoC levels.
- Develop reusable, self-checking AMS/SPICE testbenches and simulation scenarios.
- Debug complex simulation issues involving convergence, initialization, loading, stability, modeling, and analog/digital interfaces.
- Analyze circuit behavior and optimize simulations for runtime, accuracy, stability, and repeatability.
- Validate mixed-signal blocks including PMICs, PLLs, ADC/DACs, voltage references, oscillators/clocking, SerDes, and digital control logic.
- Collaborate with Analog, Digital, AMS Verification, Architecture, Modeling, and SoC teams to drive issues to closure.
Required Experience
- B.Tech/M.Tech in Electronics, Electrical Engineering, Microelectronics, or related discipline.
- 5+ years of semiconductor experience in AMS verification, SPICE simulation, or circuit-level verification.
- Strong understanding of analog circuits, mixed-signal architectures, and SPICE simulation methodologies.
- Hands-on experience with Cadence Virtuoso and waveform/debug tools such as SimVision / Verisium.
- Experience with Spectre, APS, UltraSim, XPS, or comparable SPICE/Fast-SPICE simulators.
- Exposure to Xcelium/DMSO or similar analog/digital co-simulation environments.
- Strong root-cause analysis, debugging, and simulation optimization skills.
Key Skills:
AMS | SPICE | Fast-SPICE | Spectre | APS | UltraSim | XPS | Cadence Virtuoso | Xcelium | DMSO | SimVision | Verisium | AMS Verification | Analog/Digital Co-Simulation | Convergence Debug | SoC Verification
Location-Strictly on-site inBangalore
📩 Interested candidates can apply/connect with us to discuss the opportunity.
2. Digital Mixed-Signal (DMS) Verification Engineer | 5+ Years
We are looking for an experienced Digital Mixed-Signal (DMS) Verification Engineer with strong expertise in SystemVerilog RNM, UVM, AMS/DMS verification, and behavioral modeling for complex mixed-signal IPs and SoCs.
Key Responsibilities
- Define and execute AMS/DMS verification strategies across IP, subsystem, and full-chip/SoC levels.
- Develop behavioral models using SystemVerilog Real Number Modeling (RNM), User-Defined Nets (UDNs), and related modeling techniques.
- Build and enhance UVM-based verification environments, reusable components, and automated self-checking tests.
- Verify mixed-signal designs involving PLLs, ADC/DACs, PMICs, bandgaps/references, oscillators, SerDes, analog/RF paths, and digital control/calibration logic.
- Perform mixed-signal simulations across analog models, RTL, gate-level, and SDF-annotated designs.
- Debug functional and simulation issues using Xcelium/DMSO, VCS, Virtuoso, SimVision, and related tools.
- Drive functional/code coverage, regression management, verification metrics, and closure.
- Collaborate with Analog, Digital, RF, Architecture, Modeling, and Verification teams to resolve complex design issues.
Required Experience
- B.Tech/M.Tech in Electronics, Electrical Engineering, Microelectronics, or related discipline.
- 5+ years of semiconductor industry experience in AMS/DMS verification, behavioral modeling, or mixed-signal design verification.
- Strong hands-on expertise in SystemVerilog RNM, UDNs, UVM, and mixed-signal verification methodologies.
- Experience with Cadence Xcelium/DMSO and/or Synopsys VCS.
- Experience with Cadence Virtuoso, SimVision, or comparable debug environments.
- Strong understanding of analog fundamentals, digital verification, mixed-signal architectures, coverage, regressions, and verification closure.
- Exposure to vManager, formal verification, gate-level/SDF simulation, and scripting using Python, Tcl, Perl, or Shell is advantageous.
Key Skills
DMS | AMS Verification | SystemVerilog | RNM | UDN | UVM | Xcelium | DMSO | VCS | Cadence Virtuoso | SimVision | vManager | Behavioral Modeling | SerDes | PLL | ADC/DAC | PMIC | SoC Verification | Coverage Closure
Location-Strictly on-site in Bangalore
📩 Interested candidates with relevant AMS/DMS verification expertise are invited to apply/connect with us- eng.services@dexceldesigns.com, umme.salma@dexceldesigns.com
Click on Apply to know more.
