CPU Core RTL Design Engineer
AMD
- Salary
- $126k - $217k
- Location
- Austin, Texas, United States
- Job type
- Full-time
Required skills
- Verilog
- SystemVerilog
- Python
- Tcl
About the role
Experience with Verilog/SystemVerilog RTL in CPU/SoC/ASIC environments; strong CPU architecture knowledge; logic design expertise; familiarity with synthesis, timing closure, and scripting (Python, Tcl); Bachelor's/Master's/PhD in EE or CE preferred.
About AMD
Leader in high-performance computing, graphics, and visualization technologies.
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