RTL Methodology Silicon Design Engineer
AMD
- Location
- Austin, Texas, United States
- Job type
- Full-time
Required skills
- Verilog
- SystemVerilog
- Verible
- Slang
- Verilator
- Surelog
- Python
- Perl
- Ruby
- Shell
- TCL
- Go
- Java
- C#
- TypeScript
About the role
BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field preferred; Verilog/SystemVerilog RTL development; RTL linting and static analysis; HDL parsers; AI/LLM tooling; scripting in Python, Perl, Ruby, Shell, TCL; programming in Python, Go, Java, C#, TypeScript.
About AMD
Leader in high-performance computing, graphics, and visualization technologies.
This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.
