SiliconBoard
Company:
https://www.linkedin.com/company/siliconboard
Seniority: Entry level
Industries: Semiconductor Manufacturing
Job details:
Memory Design Engineer
Location: Bengaluru | Noida | Hyderabad (On-site / Hybrid)
Employment Type: Full-time
Experience: 3+ years
Function: Semiconductor Engineering — Memory Design
About SiliconBoard
SiliconBoard connects the top 1% of semiconductor engineering talent with leading companies across the semiconductor ecosystem. This opportunity is offered through the SiliconBoard Talent Network. Shortlisted profiles are evaluated and shared with hiring companies within our partner network for relevant open positions.
About the Role
We are seeking experienced Memory Design Engineers to work on cutting-edge memory technologies — from bitcell-level circuit design to memory subsystem integration and tapeout. You will join engineering teams at leading semiconductor companies, contributing to the design, verification, and sign-off of high-performance, low-power memory products. Roles span circuit design, front-end and compiler design, and physical design, and you will be matched to opportunities based on your area of expertise.
Key Responsibilities
Memory Circuit Design
- Design and optimize memory bitcells, sense amplifiers, wordline drivers, decoders, and I/O circuits for SRAM, DRAM, Flash, or emerging NVM technologies.
- Perform transistor-level design, hand calculations, and device sizing.
- Analyze read/write margins, access time, power, leakage, noise, and variability.
- Execute PVT, mismatch, and Monte Carlo verification for memory-critical paths.
Memory Front-End & Compiler Design
- Develop RTL for memory controllers, BIST, and redundancy and repair logic.
- Contribute to memory compiler development, characterization, and validation flows.
- Drive lint, CDC, synthesis, and timing analysis for memory interface logic.
- Debug designs using simulation, logs, and waveform analysis; collaborate with architecture, verification, and physical design teams.
Memory Physical Design
- Own floorplanning, power planning, placement, CTS, and routing for memory macros and subsystems.
- Optimize power, performance, area, and density for memory arrays; resolve congestion and setup/hold timing violations.
- Support physical verification, EM/IR analysis, and implementation sign-off.
- Collaborate with circuit design, STA, DFT, and sign-off teams through tapeout.
Required Qualifications
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
- 3+ years of hands-on industry experience in memory design.
- Demonstrated depth in at least one of the following: memory circuit design (SRAM, DRAM, Flash, or embedded NVM); memory controller, BIST, or compiler design; or physical design and timing closure for memory blocks.
- Ability to articulate design decisions, trade-offs, simulation methodology, and debugging approaches from prior industry projects.
- Strong analytical, problem-solving, and communication skills.
Preferred Qualifications
- Circuit: Bitcell design, sense amplifiers, decoders, CMOS fundamentals, small-signal analysis, read/write margin analysis, leakage optimization, PVT and Monte Carlo analysis.
- Front-End: Verilog, SystemVerilog, memory controllers, BIST, redundancy and repair, CDC, synthesis, timing fundamentals.
- Physical: Floorplanning, placement, CTS, routing, STA, timing closure, congestion analysis, power planning, EM/IR, physical verification.
- Tools: Proficiency with industry-standard EDA tools such as Cadence Virtuoso, Spectre, Design Compiler, Genus, VCS, Questa, Xcelium, Innovus, ICC2, PrimeTime, HSPICE, or FineSim.
Hiring Process
- Submit your resume through the application link.
- Profiles are manually reviewed and shortlisted by our team.
- Shortlisted candidates receive an AI-based technical interview link.
- Qualified profiles are considered for relevant openings across the SiliconBoard partner network.
Additional Information
Compensation is determined by the hiring company based on role, experience, and technical readiness, in line with industry standards. Submission of an application does not guarantee an interview, referral, or employment. Profiles are evaluated on technical depth, project experience, role fit, and the requirements of participating semiconductor companies.
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