leadIC Design Pvt Ltd
Website:
leadicdesign.com
Company:
https://www.linkedin.com/company/leadicdesign
Seniority: Entry level
Industries: Semiconductors
Job details:
Company Description LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise across the complete chip development lifecycle. Founded in 2018, the company has become a trusted partner for global semiconductor leaders, delivering high-quality design services through engineering teams in India and Canada. LeadIC’s capabilities span custom, memory and analog layout, analog and mixed-signal design, digital design and RTL, design verification, physical design, STA, DFT, physical verification, IP characterization, and FPGA-based prototyping. The company emphasizes ownership-driven engineering culture, quality-focused execution, and scalable offshore teams aligned to product roadmaps. Flexible engagement models allow LeadIC to support niche technical needs or turnkey projects, building long-term technical partnerships that accelerate silicon success.
Role Description The Senior Physical Design Engineer will be responsible for end-to-end physical design implementation, from synthesis to signoff, for complex digital and mixed-signal SoCs. Day-to-day responsibilities include floorplanning, placement, CTS, routing, timing closure, power and area optimization, and close collaboration with RTL, verification, and analog teams to ensure robust integration. The engineer will drive physical verification, DFT considerations, and signoff checks, while contributing to methodology improvements, tool flows, and best practices. This is a full-time hybrid role based in Bengaluru, with a mix of on-site collaboration and some work-from-home flexibility.
Qualifications
- Strong expertise in physical design flows, including synthesis, floorplanning, placement, CTS, routing, and timing closure.
- Hands-on experience with physical verification and signoff, including DRC/LVS, power integrity, and reliability checks.
- Solid understanding of logic design principles and digital circuit behavior for high-performance, low-power designs.
- Experience with RTL design and integration, and effective collaboration with front-end design and verification teams.
- Proficiency with industry-standard EDA tools (e.g., Synopsys, Cadence, or Siemens) for PD and PV flows.
- Knowledge of STA, DFT concepts, and interaction with backend flows for testability and timing robustness.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related discipline.
- Strong analytical, problem-solving, and communication skills, with the ability to mentor junior engineers and work in cross-functional teams.
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