Mulya Technologies
Website:
mulyatech.com
Company:
https://www.linkedin.com/company/mulya-technologies
Seniority: Mid-Senior level
Industries: Engineering Services, Semiconductor Manufacturing, and Computer Hardware Manufacturing
Job details:
TITLE: RTL DESIGN ENGINEER(SMTS)
LOCATION: GREATER BENGALURU AREA
Company Description
At Tsavorite Scalable Intelligence, we are pioneering the semiconductor industry’s first Omni Processing Unit (OPU)—a breakthrough composable architecture designed to power the next generation of real-time, multi-modal Agentic AI.
Founded in 2023 by a veteran team from Intel, Nvidia, Qualcomm, and Apple, we are on a mission to eliminate the cost, power, and complexity bottlenecks of legacy GPU systems. Our technology delivers a 10x performance gain at 10% of energy consumption, scaling seamlessly from edge devices to exascale data centers.
Why Engineers Join Us:
- Architectural Innovation: Work on the MultiPlexus™ fabric, a revolutionary interconnect offering petabyte-scale bandwidth and ultra-low latency.
- Full-Stack Impact: We are building everything from modular chiplets on Samsung’s SF4X platform to our Tsavorite AI Orchestration Stack (TAOS), which provides zero-switching-cost compatibility for CUDA-optimized workflows.
- Market Momentum: We emerged from stealth with over $100 million in pre-orders from Global 500 companies and sovereign cloud providers.
Key Links to Include
- Official Website: tsavoritesi.com
- LinkedIn Page: Tsavorite Scalable Intelligence | LinkedIn
- Recent News: Tsavorite Emerges with $100M in Orders & 10x Performance (Forbes)
- https://www.businesswire.com/news/home/20251110678526/en/Tsavorite-Scalable-Intelligence
JOB DESCRIPTION:
Job Title: Design Engineer (Front-End/RTL)
Role Overview
As a Design Engineer, you will be the bridge between high-level architecture and physical
implementation. You will own the development of critical SoC subsystems/IPs, translating
complex architectural requirements into efficient, high-performance RTL. This role requires
someone who thrives on solving complex design challenges and can maintain design integrity
through the rigors of synthesis, timing, and verification.
Key Responsibilities
- Micro-architectural Definition: Translate high-level architectural requirements into
robust, detailed micro-architectural specifications.
- Design & Implementation: Develop high-quality, synthesizable RTL using Verilog and
SystemVerilog, ensuring designs meet performance, power, and area (PPA) targets.
- Strategic Analysis: Conduct deep-dive analyses of implementation options, weighing
trade-offs between latency, throughput, and silicon real estate.
- Full Front-End Flow: Drive the design through the ASIC front-end suite, including
Synthesis, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC).
- Timing Ownership: Take responsibility for timing closure to ensure the design meets
frequency targets across all corners.
- Cross-Functional Collaboration: Manage design iterations by working closely with the
Verification team and the Physical Design team
- Debugging: Root-cause complex issues across simulation, linting, CDC, and synthesis
environments.
Required Qualifications
Education & Expertise
- Degree: Bachelor’s or Master’s degree in EC/EE/CS or a related field.
- Experience: 8-14+ years of proven experience in SoC or Subsystem-level design.
- Good understanding of the AMBA protocols, specifically CHI, AXI, AHB, and APB.
- Expert-level proficiency in Verilog/SystemVerilog and micro-architecture development.
- Hands-on experience with CDC/RDC tools, Linting, and Logic Synthesis (e.g., Design compiler, Genus).
- Strong proficiency in Static Timing Analysis (STA) and timing constraints
- Good understanding of ARM architecture is desirable.
- Strong communication skills to articulate complex technical trade-offs to stakeholders
Uday
muday_bhaskar@yahoo.com
www.mulyatech.com
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